Multi-port random access memories (RAM) are substantially faster than standard RAM and commonly referred to as video random access memories (VRAM) because of their effectiveness in video systems. FIG. 1 illustrates a block diagram of a prior art multi-port memory similar to the memory described in U.S. Pat. No. 4,891,794 issued to Hush et al. entitled "Three Port Random Access Memory" assigned to the assignee of the present invention and incorporated by reference. In its simplest form, the multi-port memory includes a dynamic random access memory (DRAM) 90, a DRAM controller 92, two serial access memories (SAM) 94, 96 and a SAM controller 98. Each SAM is essentially a long shift register which can receive a block of data from the DRAM and serially shift the data out through a data port 99. The SAM can also serially shift data in through the serial port and transfer the data to the DRAM.
The DRAM is a dynamic array for storing multi-bit registers in multiple two dimensional planes each having memory cells arranged in rows and columns. The DRAM has address line inputs 95 and a plurality of input/output lines 97. Each of the registers are defined by the same row and column addresses in the multiple planes. Each SAM has a multi-bit register row associated with each of the planes of the DRAM were the columns of the DRAM correspond to the bits of the register row. In general, the DRAM and SAM's can operate either independently or in limited combinations for internal transfers of data. When operating in combination, the SAM's are structured to allow each SAM to access one row of the DRAM.
Various features have been incorporated in VRAM's to speed the transfer of data to and from an associated graphics processor or microprocessor. One example present specification, there is a need in the art for a circuit and method for block writing data to a DRAM such that the individual cells of a selected block can be written to different states, in a simultaneous fashion.